On 25 June 2026, IBM said it had built the world’s first sub-1-nanometre chip technology. The headline number is hard to ignore: a 0.7nm node, also called 7 angstroms, with close to 100 billion transistors packed onto a piece of silicon the size of a fingernail. That is roughly twice the density of the 2nm chip IBM showed back in 2021.
It reads like science fiction, and in a way it is still closer to the lab than the shop. But the part worth understanding is not the tiny number on the label. It is what IBM did to reach it, a new way of building transistors it calls nanostack, and what that really tells us about where computing goes next.
IBM's "0.7nm" is the name of a manufacturing generation, not the physical width of a transistor, and IBM says so plainly. The real breakthrough is nanostack: instead of shrinking transistors flat on the silicon, IBM stacks them vertically in three dimensions. IBM claims up to 50 percent more performance, or 70 percent better energy efficiency, than its 2nm node, with a path to production in around five years. This is a research milestone, not something you can buy.
What IBM actually announced
From its research base in Yorktown Heights, New York, IBM unveiled what it calls nanostack, described as the industry’s first three-dimensional, nanosheet-based transistor design. The chips were demonstrated at IBM’s semiconductor research complex in Albany, New York, working alongside ASML, Lam Research, Tokyo Electron and SCREEN, and using ASML’s High-NA EUV lithography to print the smallest features.
Jay Gambetta, Director of IBM Research and an IBM Fellow, put it in sweeping terms: the company is, in his words, not just making smaller transistors but reinventing how chips are built to deliver more performance and efficiency. These are the figures IBM placed on the table, and it is worth treating them as the company’s own claims rather than independently tested results.
| What IBM claims | Figure |
|---|---|
| Node name | 0.7nm, also called 7 angstroms |
| Transistor count | Close to 100 billion on a fingernail-sized chip |
| Density versus IBM 2nm (2021) | Roughly double |
| Performance | Up to 50 percent more than the 2nm node |
| Energy efficiency | Up to 70 percent better than the 2nm node |
| SRAM scaling | 40 percent demonstrated |
| Where it was built | IBM's Albany NanoTech complex, New York |
| Path to production | As early as the next five years |
First, the honest part: 0.7nm is a name, not a measurement
For most of chip history the node number described a real physical feature, the length of a transistor’s gate. That stopped being true more than a decade ago. Since around the 28nm generation, the node name has been a roadmap and marketing label rather than a ruler reading. A 0.7nm transistor is not 0.7nm across. Nothing in the chip is genuinely 7 angstroms wide, which would be only a few atoms.
IBM is refreshingly clear about this. Its own announcement states that transistor nodes now refer to a generation of manufacturing technology rather than an exact physical dimension. Holding on to that one fact is the difference between understanding the news and being dazzled by it.
So what is nanostack?
To see why nanostack matters, it helps to know how scaling has worked until now. For decades, progress meant making transistors smaller and laying more of them flat on the surface of the silicon. The shape changed along the way, from flat planar transistors to the raised fins of FinFET, then to the stacked sheets of gate-all-around. But the basic move was always the same: shrink the feature, fit more side by side.
Nanostack changes the move. Instead of only shrinking transistors and spreading them out flat, IBM builds them upward, stacking transistors in vertical layers. It uses a technique called 3D sequential integration: build one layer, bond the next on top with an ultra-thin insulating film, then repeat. Because each layer is made separately, IBM can give each one different materials and tune its speed and power on its own. The payoff is more transistors in the same footprint, even as shrinking sideways runs into the wall of physics.
Nanostack does not win by making transistors smaller. It wins by building upward in layers, the way a city grows taller once it runs out of land.
Why it matters, and who it is really for
The immediate audience for this is not gamers or laptop buyers. It is the data centre, and above all artificial intelligence. IBM points to 40 percent scaling in its SRAM, the fast on-chip memory that feeds a modern processor, and ties it directly to the bandwidth that large AI models demand. More transistors and more efficient memory in the same area is exactly what those workloads are starving for.
The wider point is about Moore’s law, the long-running observation that chips roughly double in density every couple of years. Flat shrinking has been slowing for some time. By going vertical, nanostack hands the industry a fresh direction to keep that progress alive, and IBM says its roadmap now stretches to at least another decade of scaling.
The catch: this is a milestone, not a product
A "world's first" from a research lab is a demonstration, not a release date. IBM is talking about a path to production in roughly five years, and a great deal has to go right between a working test chip in Albany and a processor in a real machine. Here is what stands between the two.
Yield and defects
A handful of working chips in a lab is not the same as making millions of them reliably and cheaply. Stacking layers on top of each other adds fresh ways for defects to creep in.
Cost
High-NA EUV machines from ASML run to hundreds of millions each, and every new node costs more than the last. Someone has to justify that spend against the gain it buys.
Heat
Stacking transistors vertically concentrates heat in a smaller volume, and pulling that heat out of a dense 3D stack is a hard problem that nobody has fully solved at scale.
Tools and design
Chip designers need software and standard building blocks that understand vertically stacked logic before they can use it. That ecosystem takes years to mature.
Who actually builds it
IBM researches and licenses technology rather than running a high-volume foundry. Turning nanostack into shipping products depends on manufacturing partners choosing to commit to it.
How it fits the bigger picture
Put nanostack on the timeline and the shape is clear. In 2021, IBM showed the world’s first 2nm chip. Now, in 2026, it is claiming the first sub-1nm node and naming the era after the angstrom rather than the nanometre. The labels keep shrinking faster than the atoms do, but the engineering underneath is real, and the direction has turned from flat to vertical.
For anyone buying a PC today, none of this is on the shelf. The best processors and graphics cards you can buy right now are built on nodes a few generations behind this, and they will be for years. If you want to know what is genuinely worth buying today, our gaming CPU guide, graphics card guide and components guide cover the parts you can actually put in a machine.
IBM’s sub-1nm chip: common questions
No. The node name is a label for a manufacturing generation, not a physical measurement, and IBM states this directly. Nothing in the chip is literally 7 angstroms across, which would be only a few atoms wide.
Not for years. This is a research demonstration at IBM's Albany facility, with a path to production that IBM puts at around five years away, and that is the optimistic case rather than a promise.
In spirit, yes. Flat shrinking has been slowing, but stacking transistors vertically gives the industry a new way to keep raising density. IBM says its roadmap now covers at least another decade.
It is a way of building transistors in vertical 3D layers instead of only shrinking them flat, so you fit more in the same area, with each layer tuned separately for speed and power.
Not directly, and not soon. The first beneficiaries are data centres and AI hardware. Any benefit for a home PC is years downstream, once the technology reaches mass production.
IBM developed it at its Albany NanoTech complex with ASML, Lam Research, Tokyo Electron and SCREEN, using ASML's High-NA EUV lithography to print the finest features.
How we read this
Hardvance is a UK retailer, not a chip fab, so we read announcements like this the way a buyer should: with real interest and a little patience. Breakthroughs at this scale matter, but they reach your desk slowly, if at all in the exact form first announced. We have stuck to IBM's own figures throughout and flagged where they are claims rather than independently tested results.
